1. Technical Field
Various embodiments relate generally to a semiconductor device and a method of manufacturing the same, and to a three-dimensional semiconductor device having a source layer and a method of manufacturing the same.
2. Related Art
A non-volatile memory device can retain data stored therein even in the absence of a power supply. As the degree of integration in creating two-dimensional memory devices that have memory cells fabricated in the form of a single layer on silicon substrates reaches a limit, suggestions of three-dimensional structured non-volatile memory devices that have memory cells vertically stacked on silicon substrates are proposed.
The structure of a known three-dimensional (3-D) non-volatile memory device is described below with reference to FIGS. 1A and 1B.
FIG. 1A is a perspective view of the structure of a conventional 3-D non-volatile memory device. FIG. 1B is a circuit diagram of a single string.
As illustrated in FIG. 1A, the conventional 3-D non-volatile memory device has a plurality of U-shaped channel layers CH each of which comprises a pipe channel layer P_CH formed in a pipe gate PG and first and second vertical channel layers V_CH coupled to the pipe channel layer P_CH. In addition, the conventional 3-D non-volatile memory device may further include word lines WL stacked one upon another and surrounding the first and second vertical channel layers V_CH, source select lines SSL and drain select lines DSL stacked over the word lines WL, a source line SL and bit lines BL.
As illustrated in FIG. 1B, a drain select transistor DST, memory cells MC, a pipe transistor P_Tr and a source select transistor SST form a single string. The string has a U shape. In the related art, since the string has a U shape, the pipe transistor P_Tr is essentially provided to couple source side memory cells MC stacked along the first vertical channel layers V_CH and drain side memory cells MC stacked along the second vertical channel layers V_CH to each other.
However, in addition to the processes of forming memory cells, another process of forming pipe transistors is also needed, thus increasing the number of processes. In addition, it may be difficult to control threshold voltages of these pipe transistors.
FIG. 2A is a perspective view of the structure of a conventional 3-D non-volatile memory device. FIG. 2B is a circuit diagram of a single string.
As illustrated in FIG. 2A, the conventional 3-D non-volatile memory device includes a lower select line LSL, word lines WL, and upper select lines USL that are stacked sequentially over a substrate SUB that includes a source region S. In addition, the conventional 3-D non-volatile memory device may further include vertical channel layers CH, memory layers (not illustrated) and bit lines BL. The vertical channel layers CH may pass through the lower select line LSL, the word lines WL, and the upper select lines USL. The memory layers may surround sidewalls of the vertical channel layers CH. The bit lines BL may be coupled to top surfaces of the vertical channel layers CH.
As illustrated in FIG. 2B, the lower select transistor LST, the memory cells MC, and the upper select transistor UST form a single string. The string may extend vertically.
However, as far as conventional 3-D non-volatile memory devices are concerned, it is not easy to perform the processes associated with the manufacturing of memory layers and vertical channel layers. Specifically, as for a known memory device, after channel holes are formed such that they pass through interlayer insulating layers and conductive layers stacked alternately, a memory layer is formed along inner surfaces of the channel holes. Subsequently, the memory layer formed on the bottom surfaces of the channel holes may be removed to expose the source region S, and the vertical channel layers CH are formed. However, it is difficult to perform the process of etching the memory layer on the bottom surfaces of the channel holes with high aspect ratios. In addition, damage to the memory layer formed along inner walls of the channel holes may occur during the etch process, thus deteriorating characteristics of the memory cells.